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rev. h a cmos, 125 mhz complete dds synthesizer ad9850 functional block diagram clock out clock out analog in analog out dac r set +v s gnd comparator phase and control words serial load 32-bit tuning word high speed dds frequency/phase data register parallel load data input register ad9850 10-bit dac ref clock in master reset word load clock frequency update/ data register reset 1-bit 40 loads 8-bits 5 loads frequency, phase, and control data input general description the ad9850 is a highly integrated device that uses advanced dds technology coupled with an internal high speed, high performance d/a converter and comparator to form a com- plete, digitally programmable frequency synthesizer and clock generator function. when referenced to an accurate clock source, the ad9850 generates a spectrally pure, fre- quency/phase programmable, analog output sine wave. this sine wave can be used directly as a frequency source, or it can be converted to a square wave for agile-clock generator applica- tions. the ad 9850? innovative high speed dds core provides a 32-bit frequency tuning word, which results in an output tuning resolution of 0.0291 hz for a 125 mhz reference clock input. the ad 9850? circuit architecture allows the generation of output frequencies of up to one-half the reference clock frequency (or 62.5 mhz), and the output frequency can be digi- tally changed (asynchronously) at a rate of up to 23 million new frequencies per second. the device also provides five bits of digitally con trolled phase modulation, which enables phase shifting of its output in increments of 180 , 90 , 45 , 22.5 , 11.25 , and any combination thereof. the ad9850 also contains a high speed comparator that can be configured to accept the (externally) filtered output of the dac to generate a low jitter square wave output. this facilitates the device? use as an agile clock generator function. the frequency tuning, control, and phase modulation words are loaded into the ad9850 via a parallel byte or serial loading format. the parallel load format consists of five iterative loads of an 8-bit control word (byte). the first byte controls phase modulation, power-down enable, and loading format; bytes 2 to 5 comprise the 32-bit frequency tuning word. serial loading is accomplished via a 40-bit serial data stream on a single pin. the ad9850 complete dds uses advanced cmos technology to provide this breakthrough level of functionality and performance on just 155 mw of power dissipation (3.3 v supply). the ad9850 is available in a space-saving 28-lead ssop, surface-mount package. it is specified to operate over the extended industrial temperature range of ?0 c to +85 c. features 125 mhz clock rate on-chip high performance dac and high speed comparator dac sfdr > 50 db @ 40 mhz a out 32-bit frequency tuning word simplified control interface: parallel byte or serial loading format phase modulation capability 3.3 v or 5 v single-supply operation low power: 380 mw @ 125 mhz (5 v) low power: 155 mw @ 110 mhz (3.3 v) power-down function ultrasmall 28-lead ssop packaging applications frequency/phase?gile sine wave synthesis clock recovery and locking circuitry for digital communications digitally controlled adc encode generator agile local oscillator applications information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2004 analog devices, inc. all rights reserved.
ad9850brs parameter temp test level min typ max unit clock input characteristics frequency range 5 v supply full iv 1 125 mhz 3.3 v supply full iv 1 110 mhz pulse width high/low 5 v supply 25 civ 3.2 ns 3.3 v supply 25 civ 4.1 ns dac output characteristics full-scale output current r set = 3.9 k 25 cv 10.24 ma r set = 1.95 k 25 cv 20.48 ma gain error 25 ci e10 +10 % fs gain temperature coefficient full v 150 ppm/ c output offset 25 ci 10 a output offset temperature coefficient full v 50 na/ c differential nonlinearity 25 ci 0.5 0.75 lsb integral nonlinearity 25 ci 0.5 1 lsb output slew rate (50 , 2 pf load) 25 cv 400 v/ s output impedance 25 civ 50 120 k output capacitance 25 civ 8 pf voltage compliance 25 ci 1.5 v spurious-free dynamic range (sfdr) wideband (nyquist bandwidth) 1 mhz analog out 25 civ 637 2 dbc 20 mhz analog out 25 civ 505 8 dbc 40 mhz analog out 25 civ 465 4 dbc narrowband 40.13579 mhz 50 khz 25 civ 8 0 dbc 40.13579 mhz 200 khz 25 civ 7 7 dbc 4.513579 mhz 50 khz/20.5 mhz clk 25 civ 8 4 dbc 4.513579 mhz 200 khz/20.5 mhz clk 25 civ 8 4 dbc comparator input characteristics input capacitance 25 cv 3 pf input resistance 25 civ 500 k input current 25 ci e12 +12 a input voltage range 25 civ 0 v dd v comparator offset * full vi 30 30 mv comparator output characteristics logic 1 voltage 5 v supply full vi 4.8 v logic 1 voltage 3.3 v supply full vi 3.1 v logic 0 voltage full vi 0.4 v propagation delay, 5 v supply (15 pf load) 25 cv 5.5 ns propagation delay, 3.3 v supply (15 pf load) 25 cv 7 ns rise/fall time, 5 v supply (15 pf load) 25 cv 3 ns rise/fall time, 3.3 v supply (15 pf load) 25 cv 3.5 ns output jitter (p-p) 25 cv 80 ps clock output characteristics clock output duty cycle (clk gen. config.) 25 civ 50 10 % rev. h e2e (v s = 5 v 5% except as noted, r set = 3.9 k ) ad9850especifications
ad9850brs parameter temp test level min typ max unit cmos logic inputs (including clkin) logic 1 voltage, 5 v supply 25 ci 3.5 v logic 1 voltage, 3.3 v supply 25 civ 2.4 v logic 0 voltage 25 civ 0.8 v logic 1 current 25 ci 12 a logic 0 current 25 ci 12 a input capacitance 25 cv 3 pf power supply (a out = 1/3 clkin) +v s current @ 62.5 mhz clock, 3.3 v supply full vi 30 48 ma 110 mhz clock, 3.3 v supply full vi 47 60 ma 62.5 mhz clock, 5 v supply full vi 44 64 ma 125 mhz clock, 5 v supply full vi 76 96 ma p diss @ 62.5 mhz clock, 3.3 v supply full vi 100 160 mw 110 mhz clock, 3.3 v supply full vi 155 200 mw 62.5 mhz clock, 5 v supply full vi 220 320 mw 125 mhz clock, 5 v supply full vi 380 480 mw p diss power-down mode 5 v supply full v 30 mw 3.3 v supply full v 10 mw * tested by measuring output duty cycle variation. specifications subject to change without notice. timing characteristics * ad9850brs parameter temp test level min typ max unit t ds (data setup time) full iv 3.5 ns t dh (data hold time) full iv 3.5 ns t wh (w_clk minimum pulse width high) full iv 3.5 ns t wl (w_clk minimum pulse width low) full iv 3.5 ns t wd (w_clk delay after fq_ud) full iv 7.0 ns t cd (clkin delay after fq_ud) full iv 3.5 ns t fh (fq_ud high) full iv 7.0 ns t fl (fq_ud low) full iv 7.0 ns t cf (output latency from fq_ud) frequency change full iv 18 clkin cycles phase change full iv 13 clkin cycles t fd (fq_ud minimum delay after w_clk) full iv 7.0 ns t rh (clkin delay after reset rising edge) full iv 3.5 ns t rl (reset falling edge after clkin) full iv 3.5 ns t rs (minimum reset width) full iv 5 clkin cycles t ol (reset output latency) full iv 13 clkin cycles t rr (recovery from reset) full iv 2 clkin cycles wake-up time from power-down mode 25 cv 5 s * control functions are asynchronous with clkin. specifications subject to change without notice. (v s = 5 v 5% except as noted, r set = 3.9 k ) rev. h e3e ad9850
ad9850 e4e rev. h absolute maximum ratings * maximum junction temperature . . . . . . . . . . . . . . . . 150 c v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 v digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . e0.7 v to +v s digital output continuous current . . . . . . . . . . . . . . . 5 ma dac output current . . . . . . . . . . . . . . . . . . . . . . . . . 30 ma storage temperature . . . . . . . . . . . . . . . . . . e65 c to +150 c operating temperature . . . . . . . . . . . . . . . . . e40 c to +85 c lead temperature (soldering 10 sec) . . . . . . . . . . . . . 300 c ssop ja thermal impedance . . . . . . . . . . . . . . . . . . 82 c/w * absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability under any of these conditions is not necessarily implied. exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. explanation of test levels test level i 100% production tested. iii sample tested only. iv parameter is guaranteed by design and characterization testing. v parameter is a typical value only. vi all devices are 100% production tested at 25 c. 100% production tested at temperature extremes for military temperature devices; guaranteed by design and characterization testing for industrial devices. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9850 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. application note : users are cautioned not to apply digital input signals prior to power-up of this device. doing so may r esult in a latch-up condition. ordering guide model temperature range package description package option ad9850brs e40 c to +85 c shrink small outline package (ssop) rs-28 ad9850brs-reel e40 c to +85 c shrink small outline package (ssop) rs-28 ad9850brsz * e40 c to +85 c shrink small outline package (ssop) rs-28 ad9850brsz-reel * e40 c to +85 c shrink small outline package (ssop) rs-28 ad9850/cgpcb evaluation board clock generator ad9850/fspcb evaluation board frequency synthesizer * z = pb-free part. warning! esd sensitive device
ad9850 e5e rev. h pin configuration 17 16 15 20 19 18 28 27 26 25 24 23 22 21 14 13 12 11 10 9 8 1 2 3 4 7 6 5 top view (not to scale) ad9850 d3 d7 msb/serial load d6 d5 d4 d2 d1 lsb d0 reset dvdd dgnd dgnd dvdd w clk fq ud clkin agnd agnd ioutb iout avdd r set qoutb qout avdd vinn vinp dacbl (nc) nc = no connect table i. pin function descriptions pin no. mnemonic function 4 to 1, d0 to d7 8-bit data input. this is the 8-bit data port for iteratively loading the 32-bit frequency and the 8-bit phase/ 28 to 25 control word. d7 = msb; d0 = lsb. d7 (pin 25) also serves as the input pin for the 40-bit ser ial data-word. 5, 24 dgnd digital ground. these are the ground return leads for the digital circuitry. 6, 23 dvdd supply voltage leads for digital circuitry. 7w _clk word load clock. this clock is used to load the parallel or serial frequency/phase/control words. 8 fq_ud frequency update. on the rising edge of this clock, the dds updates to the frequency (or phase) loaded in the data input register; it then resets the pointer to word 0. 9 clkin reference clock input. this may be a continuous cmos-level pulse train or sine input biased at 1/2 v supply. the rising edge of this clock initiates operation. 10, 19 agnd analog ground. these leads are the ground return for the analog circuitry (dac and comparator). 11, 18 avdd supply voltage for the analog circuitry (dac and comparator). 12 r set dac?s external r set connection. this resistor value sets the dac full-scale output current. for normal applications ( f s i out = 10 ma), the value for r set is 3.9 k connected to ground. the r set /i out relationship is i out = 32 (1.248 v/ r set ). 13 qoutb output complement. this is the comparator?s complement output. 14 qout output true. this is the comparator?s true output. 15 vinn inverting voltage input. this is the comparator?s negative input. 16 vinp noninverting voltage input. this is the comparator?s positive input. 17 dacbl (nc) dac baseline. this is the dac baseline voltage reference; this lead is internally bypassed and should normally be considered a no connect for optimum performance. 20 ioutb complementary analog output of the dac. 21 iout analog current output of the dac. 22 reset reset. this is the master reset function; when set high, it clears all registers (except the input register), and the dac output goes to cosine 0 after additional clock cycles?see figure 7.
ch1 s spectrum 10db/ref e8.6dbm 76.642 db fxd ad9850 clock 125mhz rbw # 100hz start 0hz vbw 100hz atn # 30db swp 762 sec stop 62.5mhz 0 tpc 1. sfdr, clkin = 125 mhz/f out = 1 mhz ch1 ss pectrum 10db/ref e10dbm 54.818 db fxd ad9850 clock 125mhz rbw # 300hz start 0hz vbw 300hz atn # 30db swp 182.6 sec stop 62.5mhz 0 tpc 2. sfdr, clkin = 125 mhz/f out = 41 mhz tek run: 100gs/s et sample ch 1 500mv m 20.0ns ch 1 1.58v d 500ps runs after 1 : 300ps @: 25.26ns tpc 3. typical comparator output jitter, ad9850 configured as clock generator with 42 mhz lp filter (40 mhz a out /125 mhz clkin) ad9850etypical performance characteristics e6e rev. h ch1 s spectrum 10db/ref e10dbm 59.925 db fxd ad9850 clock 125mhz rbw # 300hz start 0hz vbw 300hz atn # 30db swp 182.6 sec stop 62.5mhz 0 tpc 4. sfdr, clkin = 125 mhz/f out = 20 mhz ch1 s spectrum 12db/ref 0dbm e85.401 db mkr ad9850 rbw # 3hz center 4.513579mhz vbw 3hz atn # 20db swp 399.5 sec span 400khz 0 e23 khz tpc 5. sfdr, clkin = 20.5 mhz/f out = 4.5 mhz offset from 5mhz carrier e hz e105 e110 e155 e115 e120 e125 e130 e135 e140 e145 e150 100 100k 1k dbc 10k pn.3rd tpc 6. output residual phase noise (5 mhz a out /125 mhz clkin)
ad9850 e7e rev. h tek run: 50.0gs/s et average ch1 1.00v m 1.00ns ch 1 1.74v ch 1 rise 2.870ns 1 tpc 7. comparator output rise time (5 v supply/15 pf load) clkin e mhz 0 140 20 40 60 80 100 120 68 52 sfdr e db 66 60 58 56 54 64 62 v cc = 5v v cc = 3.3v f out = 1/3 of clkin tpc 8. sfdr vs. clkin frequency (a out = 1/3 of clkin) frequency out e mhz 90 80 30 040 10 supply current e ma 20 30 70 60 50 40 v cc = 5v v cc = 3.3v tpc 9. supply current vs. a out frequency (clkin = 125/110 mhz for 5 v/3.3 v plot) tek run: 50.0gs/s et average ch1 1.00v m 1.00ns ch 1 1.74v ch 1 fall 3.202ns 1 tpc 10. comparator output fall time (5 v supply/15 pf load) clock frequency e mhz 0 140 20 40 60 80 100 120 90 10 supply current e ma 80 50 40 30 20 70 60 v cc = 5v v cc = 3.3v tpc 11. supply current vs. clkin frequency (a out = 1/3 of clkin) dac i out e ma 75 70 45 20 5 sfdr e db 10 15 65 60 55 50 f out = 1mhz f out = 40mhz f out = 20mhz tpc 12. sfdr vs. dac i out (a out = 1/3 of clkin)
ad9850 e8e rev. h +v s data bus low-pass filter gnd processor xtal osc clk ioutb vinn vinp qout qoutb iout 100k 100k 200 100 470pf 200 comp true cmos clock outputs rset ad9850 5-pole elliptical 42mhz low-pass 200 impedance 8-b 5 parallel data, or 1-b 40 serial data, reset, and 2 clock lines figure 1. basic ad9850 clock generator application with low-pass filter vca rx if in adc encode i/q mixer and low-pass filter i q 8 8 ad9059 dual 8-bit adc digital demodulator rx baseband digital data out adc clock frequency locked to tx chip/ symbol pn rate ad9850 clock generator 32 chip/symbol/pn rate data 125mhz reference clock agc figure 2. ad9850 clock generator application in a spread-spectrum receiver theory of operation and application the ad9850 uses direct digital synthesis (dds) technology, in the form of a numerically controlled oscillator, to generate a frequency/ phase-agile sine wave. the digital sine wave is converted to analog form via an internal 10-bit high speed d/a converter, and an on-board high speed comparator is provided to translate the analog sine wave into a low jitter ttl/cmos compatible output square wave. dds technology is an innovative circuit architecture that allows fast and precise manipulation of its output frequency under full digital control. dds also enables very high resolution in the incremental selection of output frequency; the ad9850 allows an output frequency resolution of 0.0291 hz with a 125 mhz refer- ence clock applied. the ad9850?s output waveform is phase con- tinuous when changed. the basic functional block diagram and signal flow of the ad9850 configured as a clock generator is shown in figure 4. the dds circuitry is basically a digital frequency divider function whose incremental resolution is determined by the frequency of the reference clock divided by the 2 n number of bits in the tuning word. the phase accumulator is a variable-modulus counter that increments the number stored in it each time it rec eives a clock pulse. when the counter overflows, it wraps around, making the phase accumulator?s output contiguous. the frequency tuning word sets the modulus of the counter, which effectively determines the size of the increment ( phase) that is added to the value in the phase accumulator on the next clock pulse. the larger the added increment, the faster the accumulator overflows, which results in a higher output fre- quency. the ad9850 uses an innovative and proprietary algorithm that mathematically converts the 14-bit truncated value of the phase accumulator to the appropriate cos value. this unique algorithm uses a much reduced rom look-up table and dsp techniques to perform this function, which contributes to the small size and low power dissipation of the ad9850. the relationship of the output frequency, reference clock, and tuning word of the ad9850 is determined by the formula f out = ( phase clkin )/2 32 where: phase is the value of the 32-bit tuning word. clkin is the input reference clock frequency in mhz. f out is the frequency of the output signal in mhz. the digital sine wave output of the dds block drives the inter- nal high speed 10-bit d/a converter that reconstructs the sine wave in analog form. this dac has been optimized for dynamic performance and low glitch energy as manifested in the low jitter performance of the ad9850. because the output of the if frequency in tuning word ad9850 complete dds 125mhz reference filter rf frequency out filter 3a. frequency/phaseeagile local oscillator tuning word ad9850 complete dds 125mhz reference clock filter rf frequency out phase comparator loop filter vco divide-by-n 3b. frequency/phaseeagile reference for pll tuning word ref frequency rf frequency out phase comparator loop filter vco filter programmable divide-by-n function ad9850 complete dds 3c. digitally-programmable divide-by-n function in pll figure 3. ad9850 complete dds synthesizer in frequency up-conversion applications
ad9850 e9e rev. h clk out phase accumulator tuning word specifies output frequency as a fraction of ref clock frequency n amplitude/cos conv. algorithm dds circuitry d/a converter lp comparator ref clock in digital domain cos (x) figure 4. basic dds block diagram and signal flow of ad9850 and automatically places itself in the power-down mode. when in this state, if the clock frequency again exceeds the threshold, the device resumes normal operation. this shutdown mode prevents excessive current leakage in the dynamic registers of the device. the d/a converter output and comparator inputs are available as differential signals that can be flexibly configured in any manner desired to achieve the objectives of the end system. the typical application of the ad9850 is with single-ended output/ input analog signals, a single low-pass filter, and the generation of the comparator reference midpoint from the differential dac output as shown in figure 1. programming the ad9850 the ad9850 contains a 40-bit register that is used to program the 32-bit frequency control word, the 5-bit phase modulation word, and the power-down function. this register can be loaded in a parallel or serial mode. in the parallel load mode, the register is loaded via an 8-bit bus; the full 40-bit word requires five iterations of the 8-bit word. the w_clk and fq_ud signals are used to address and load the registers. the rising edge of fq_ud loads the (up to) 40-bit control data-word into the device and resets the address pointer to the first register. subsequent w_clk rising edges load the 8 -bit data on words [7:0] and move the pointer to the next register. after five loads, w_clk edges are ignored until either a reset or an fq_ud rising edge resets the address pointer to the first register. in serial load mode, subsequent rising edges of w_clk shift the 1-bit data on pin 25 (d7) through the 40 bits of program- ming information. after 40 bits are shifted through, an fq_ud pulse is required to update the output frequency (or phase). the function assignments of the data and control words are shown in table iii; the detailed timing sequence for updating the output frequency and/or phase, resetting the device, and powering up/down, are shown in the timing diagrams of figures 6 through 12. note: there are specific control codes, used for factory test purposes, that render the ad9850 temporarily inoperable. the user must take deliberate precaution to avoid inputting the codes listed in table ii. ad9850 is a sampled signal, its output spectrum follows the nyquist sampling theorem. specifically, its output spectrum contains the fundamental plus aliased signals (images) that occur at multiples of the reference clock frequency the selected output frequency. a graphical representation of the sampled spectrum, with aliased images, is shown in figure 5. 20mhz fundamental 80mhz 1st image 120mhz 2nd image 180mhz 3rd image 220mhz 4th image 280mhz 5th image 100mhz reference clock frequency fc fc + fo fc e fo 2fc e fo 2fc + fo 3fc e fo f out si n(x )/ x envelope x=( )fo/fc signal amplitude figure 5. output spectrum of a sampled signal in this example, the reference clock is 100 mhz and the output frequency is set to 20 mhz. as can be seen, the aliased images are very prominent and of a relatively high energy level as deter- mined by the sin(x)/x roll-off of the quantized d/a converter output. in fact, depending on the fo/reference clock relation- ship, the first aliased image can be on the order of e3 db below the fundamental. a low-pass filter is generally placed between the out put of the d/a converter and the input of the com- parator to further suppress the effects of aliased images. obvi- ously, cons ideration must be given to the relationship of the selected output frequency and the reference clock frequency to avoid unwanted (and unexpected) output anomalies. to apply the ad9850 as a clock generator, limit the selected output frequency to <33% of reference clock frequency, and thereby avoid generating aliased signals that fall within, or close to, the output band of interest (generally dc-selected output fre- quency). this practice eases the complexity (and cost) of the external filter requirement for the clock generator application. the reference clock frequency of the ad9850 has a minimum limitation of 1 mhz. the device has internal circuitry that senses when the minimum clock rate threshold has been exceeded
ad9850 e10e rev. h t ds w0 * w1 w2 w3 w4 t dh t wh t wl t cf valid data old freq (phase) new freq (phase) * output update can occur after any word load and is asynchronous with the reference clock data w clk clkin cos out t ds data setup time 3.5ns t dh data hold time 3.5ns t wh w clk high 3.5ns t wl w clk low 3.5ns t cd clk delay after fq_ud 3.5ns t fh fq ud high 7.0ns t fl fq ud low 7.0ns t fd fq ud delay after w clk 7.0ns t cf output latency from fq ud frequency change 18 clock cycles phase change 13 clock cycles symbol definition minimum t cd t fd t fh t fl fq ud figure 6. parallel load frequency/phase update timing sequence table iii. 8-bit parallel load data/control word functional assignment word data[7] data[6] data[5] data[4] data[3] data[2] data[1] data[0] w0 phase-b4 phase-b3 phase-b2 phase-b1 phase-b0 power-down control control (msb) (lsb) w1 freq-b31 freq-b30 freq-b29 freq-b28 freq-b27 freq-b26 freq-b25 freq-b24 (msb) w2 freq-b23 freq-b22 freq-b21 freq-b20 freq-b19 freq-b18 freq-b17 freq-b16 w3 freq-b15 freq-b14 freq-b13 freq-b12 freq-b11 freq-b10 freq-b9 freq-b8 w4 freq-b7 freq-b6 freq-b5 freq-b4 freq-b3 freq-b2 freq-b1 freq-b0 (lsb) table ii. factory reserved internal test control codes loading format factory reserved codes parallel 1) w0 = xxxxxx10 2) w0 = xxxxxx01 serial 1) w32 = 1; w33 = 0 2) w32 = 0; w33 = 1 3) w32 = 1; w33 = 1
ad9850 e11e rev. h t rh clk delay after reset rising edge 3.5ns t rl reset falling edge after clk 3.5ns t rr recovery from reset 2 clk cycles t rs minimum reset width 5 clk cycles t ol reset output latency 13 clk cycles symbol definition minimum results of reset: e frequency/phase register set to 0 e address pointer reset to w0 e power-down bit reset to 0 e data input register uneffected t rh t rl t rr t rs t ol cos (0) clkin cos out reset note: the timing diagram above shows the minimal amount of reset time needed before writing to the device. however, the master reset does not have to be synchronous with the clkin if the minimal time is not required. figure 7. master reset timing sequence xxxxx100 data (w0) w clk fq ud clkin internal clocks disabled dac strobe figure 8. parallel load power-down sequence/internal operation xxxxx000 data (w0) w clk fq ud clkin internal clocks enabled figure 9. parallel load power-up sequence/internal operation
ad9850 e12e rev. h xxxxx011 data (w0) (parallel) w clk fq ud note: w32 and w33 should always be set to 0. data (serial) required to reset control registers note: for device start-up in serial mode, hardwire pin 2 at 0, pin 3 at 1, and pin 4 at 1 (see figure 11). w32 = 0 w33 = 0 enable serial mode load 40-bit serial word figure 10. serial load enable sequence +v supply 3 4 2 ad9850brs figure 11. pins 2 to 4 connection for default serial mode operation data e w clk fq ud w0 w1 w2 w3 w39 40 w clk cycles figure 12. serial load frequency/phase update sequence table iv. 40-bit serial load word function assignment w0 freq-b0 (lsb) w1 freq-b1 w2 freq-b2 w3 freq-b3 w4 freq-b4 w5 freq-b5 w6 freq-b6 w7 freq-b7 w8 freq-b8 w9 freq-b9 w10 freq-b10 w11 freq-b11 w12 freq-b12 w13 freq-b13 w28 freq-b28 w29 freq-b29 w30 freq-b30 w31 freq-b31 (msb) w32 control w33 control w34 power-down w35 phase-b0 (lsb) w36 phase-b1 w37 phase-b2 w38 phase-b3 w39 phase-b4 (msb) w14 freq-b14 w15 freq-b15 w16 freq-b16 w17 freq-b17 w18 freq-b18 w19 freq-b19 w20 freq-b20 w21 freq-b21 w22 freq-b22 w23 freq-b23 w24 freq-b24 w25 freq-b25 w26 freq-b26 w27 freq-b27
ad9850 e13e rev. h data (7) e w clk fq ud w32 = 0 w33 = 0 w34 = 1 w35 = x w36 = x w37 = x w38 = x w39 = x figure 13. serial load power-down sequence v cc qout/ qoutb v cc iout ioutb vinp/ vinn v cc digital in v cc dac output comparator output comparator input digital inputs figure 14. ad9850 i/o equivalent circuits pcb layout information the ad9850/cgpcb and ad9850/fspcb evaluation boards (figures 15 through 18) represent typical implementations of the ad9850 and exemplify the use of high frequency/high resolution design and layout practices. the printed circuit board that con tains the ad9850 should be a multilayer board that allows dedicated power and ground planes. the power and ground planes should be free of etched traces that cause discontinuities in the planes. it is recommended that the top layer of the multilayer board also contain an interspatial ground plane, which makes ground avail- able for surface-mount devices. if separate analog and digital system ground planes exist, they should be connected together at the ad9850 for optimum results. avoid running digital lines under the device because these couple noise onto the die. the power supply lines to the ad9850 should use as large a track as possible to provide a low impedance path and reduce the effects of glitches on the power supply line. fast switching signals like clocks should be shielded with ground to avoid radiating noise to other sections of the board. avoid crossover of digital and analog signal paths. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the cir- cuit board. use microstrip techniques where possible. good decoupling is also an important consideration. the analog (avdd) and digital (dvdd) supplies to the ad9850 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. all analog and digital supplies should be decoupled to agnd and dgnd, respectively, with high quality ceramic capacitors. to achieve best performance from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. in systems where a common supply is used to drive both the avdd and dvdd supplies of the ad9850, it is recommended that the system?s avdd supply be used. analog devices, inc. applications engineering support is avail- able to answer additional questions on grounding and pcb layout. call 1-800-analogd or contact us at www.analog.com/dds. evaluation boards two versions of evaluation boards are available for the ad9850, which facilitate the implementation of the device for bench- top analysis and serve as a reference for pcb layout. the ad9850/fspcb is used in applications where the device is used primarily as a frequency synthesizer. this version facilitates connection of the ad9850?s internal d/a converter output to a 50 spectrum analyzer input; the internal comparator on the ad9850 dut is not enabled (see figure 15 for an electrical schematic of ad9850/fspcb). the ad9850/cgpcb is used in applications using the device in the clock generator mode. it connects the ad9850?s dac output to the internal comparator input via a single-ended, 42 mhz low-pass, 5-pole elliptical filter. this model facilitates the access of the ad9850?s com- parator output for evaluation of the device as a frequency- and phase-agile clock source (see figure 17 for an electrical sche- matic of ad9850/cgpcb). both versions of the ad9850 evaluation board are designed to interface to the parallel printer port of a pc. the operating software runs under microsoft windows and provides a user- friendly and intuitive format for controlling the functionality and observing the performance of the device. the 3.5 inch floppy provided with the evaluation board contains an execut- able file that loads and displays the ad9850 function-selection screen. the evaluation board can be operated with 3.3 v or 5 v supplies. the evaluation boards are configured at the factory for an external reference clock input; if the on-board crystal clock source is used, remove r2.
ad9850 e14e rev. h ad9850 evaluation board instructions required hardware/software ? ibm compatible computer operating in a windows environment. ? printer port, 3.5 inch floppy drive, and centronics compatible printer cable. ? xtal clock or signal generator?if using a signal generator, dc offset the signal to one-half the supply voltage and apply at least 3 v p-p signal across the 50 (r2) input resistor. remove r2 for high z clock input. ? ad9850 evaluation board software disk and ad9850/fspcb or ad9850/cgpcb evaluation board. ? 5 v voltage supply. setup 1. copy the contents of the ad9850 disk onto your hard drive (there are three files). 2. connect the printer cable from your computer to the ad9850 evaluation board. 3. apply power to ad9850 evaluation board. the ad9850 is powered separately from the connector marked dut +v. the ad9850 may be powered with 3.3 v to 5 v. 4. connect external 50 clock or remove r2 and apply a high z input clock such as a crystal can oscillator. 5. locate the file called 9850rev2.exe and execute that program. 6. monitor should display a control panel to allow operation of the ad9850 evaluation board. operation on the control panel, locate the box called computer i/o. point to and click the selection marked lpt1 and then point to the test box and click. a message will appear telling users if their choice of output ports is correct. choose other ports as necessary to achieve a correct setting. if they have trouble get- ting their computer to recognize any printer port, they should try the following: connect three 2 k pull-up resistors from pins 9, 8, and 7 of u3 to 5 v. this will assist weak printer port out- puts in driving the heavy capacitance load of the printer cable. if troubles persist, try a different printer cable. locate the master reset button with the mouse and click it. this will reset the ad9850 to 0 hz, 0 phase. the output should be a dc voltage equal to the full-scale output of the ad9850. locate the clock box and place the cursor in the frequency box. type in the clock frequency (in mhz) that the user will be applying to the ad9850. click the load button or press enter on the keyboard. move the cursor to the output frequency box and type in the desired output frequency (in mhz). click the load button or press the enter key. the bus monitor section of the control panel will show the 32-bit word that was loaded into the ad9850. upon completion of this step, the ad9850 output should be active and outputting the user's frequency information. changing the output phase is accomplished by clicking on the down arrow in the output phase delay box to make a selection and then clicking the load button. other operational modes (frequency sweeping, sleep, serial input) are available to the user via keyboard/mouse control. the ad9850/fspcb provides access into and out of the on-chip comparator via test point pairs (each pair has an active input and a ground connection). the two active inputs are labeled tp1 and tp2. the unmarked hole next to each labeled test point is a ground connection. the two active outputs are labeled tp5 and tp6. unmarked ground connections are adjacent to each of these test points. the ad9850/cgpcb provides bnc inputs and outputs associ- ated with the on-chip comparator and the on-board, fifth-order, 200 input/output z, elliptic, 45 mhz, low-pass filter. jumpering (soldering a wire) e1 to e2, e3 to e4, and e5 to e6 connects the on-board filter and the midpoint switching voltage to the com- parator. users may elect to insert their own filter and compara- tor threshold voltage by removing the jumpers and inserting a filter between j7 and j6 and then providing a threshold voltage at e1. if users choose to use the xtal socket to supply the clock to the ad9850, they must remove r2 (a 50 chip resistor). the crys tal oscillator must be either ttl or cmos (prefer- ably) compatible.
ad9850 e15e rev. h j6 r1 3.9k r5 25 17 16 15 20 19 18 28 27 26 25 24 23 22 21 14 13 12 11 10 9 8 1 2 3 4 7 6 5 u1 ad9850 d3 d2 d1 dgnd dvdd w clk fq ud clkin agnd avdd r set qout qoutb d0 d7 d6 d5 d4 reset dvdd dgnd agnd ioutb iout avdd vinn vinp dacbl d3 d2 d1 d0 gnd +v d7 d6 d5 d4 +v gnd reset gnd wclk clkin gnd +v fqud +v 10ma r set tp5 tp6 tp7 tp8 gnd gnd gnd gnd tp1 tp2 tp3 tp4 r4 50 dac out to 50 comparator inputs r6 1k r7 1k gnd +v comparator outputs 14 vcc +5v r2 50 j5 clkin remove when using y1 8 out xtal osc gnd y1 7 reset wclk fqud check rreset wwclk ffqud rreset 12 13 14 15 16 17 18 19 8q 7q 6q 5q 4q 3q 2q 1q 8d 7d 6d 5d 4d 3d 2d 1d 9 8 7 6 5 4 3 2 u3 74hct574 clk oe 11 1 strobe c36crpx j1 d0 d1 d2 d3 d4 d5 d6 d7 12 13 14 15 16 17 18 19 8q 7q 6q 5q 4q 3q 2q 1q 8d 7d 6d 5d 4d 3d 2d 1d 9 8 7 6 5 4 3 2 u2 74hct574 clk oe 11 1 strobe rreset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 ffqud wwclk strobe check p o r t 1 +v 5v c2 0.1 f c3 0.1 f c4 0.1 f c5 0.1 f c8 0.1 f c9 0.1 f c10 0.1 f c6 10 f c7 10 f +v 5v j2 j3 j4 banana jacks +v 5v gnd h1 no. 6 h2 no. 6 h3 no. 6 h4 no. 6 mounting holes r10 2.2k 5v rreset r9 2.2k ffqud r8 2.2k wwclk r3 2.2k strobe figure 15. ad9850/fspcb electrical schematic component list integrated circuits u1 ad9850brs (28-lead ssop) u2, u3 74hct574 h-cmos octal flip-flop capacitors c2 to c5, c8 to c10 0.1 f ceramic chip capacitor c6, c7 10 f tantalum chip capacitor resistors r1 3.9 k resistor r2, r4 50 resistor r3, r8, r9, r10 2.2 k resistor r5 25 resistor r6, r7 1 k resistor connectors j1 36-pin d connector j2, j3, j4 banana jack j5, j6 bnc connector
ad9850 e16e rev. h 16a. ad9850/fspcb top layer 16b. ad9850/fspcb ground plane figure 16. ad9850/fspcb evaluation board layout 16c. ad9850/fspcb power plane 16d. ad9850/fspcb bottom layer
ad9850 e17e rev. h c36crpx j1 d0 d1 d2 d3 d4 d5 d6 d7 12 13 14 15 16 17 18 19 8q 7q 6q 5q 4q 3q 2q 1q 8d 7d 6d 5d 4d 3d 2d 1d 9 8 7 6 5 4 3 2 u2 74hct574 clk oe 11 1 strobe rreset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 ffqud wwclk strobe check p o r t 1 +v 5v c2 0.1 f c3 0.1 f c4 0.1 f c5 0.1 f c8 0.1 f c9 0.1 f c10 0.1 f c6 10 f c7 10 f +v 5v bnc r1 3.9k r8 100 17 16 15 19 18 20 28 27 26 25 24 23 22 21 14 13 12 11 10 9 8 1 2 3 4 7 6 5 u1 ad9850 d3 d2 d1 dgnd dvdd w clk fq ud clkin agnd avdd r set qout qoutb d0 d7 d6 d5 d4 reset dvdd dgnd agnd ioutb iout avdd vinn vinp dacbl d3 d2 d1 d0 gnd +v wclk clkin gnd +v fqud d7 d6 d5 d4 +v gnd reset gnd +v e3 e4 e2 e1 r6 200 bnc bnc c1 470pf j6 r5 100k r4 100k e5 e6 c11 22pf c12 3.3pf 1 2 l1 1008cs 910nh c13 33pf c14 8.2pf 1 2 l2 1008cs 680nh c15 22pf r7 200 j9 j7 200 z 42mhz elliptic low-pass filter 10ma r set j8 h1 no. 6 h2 no. 6 h3 no. 6 h4 no. 6 mounting holes reset wclk fqud check rreset wwclk ffqud rreset 12 13 14 15 16 17 18 19 8q 7q 6q 5q 4q 3q 2q 1q 8d 7d 6d 5d 4d 3d 2d 1d 9 8 7 6 5 4 3 2 u3 74hct574 clk oe 11 1 strobe j2 j3 j4 banana jacks +v 5v gnd 14 vcc 5v r2 50 j5 clkin remove when using y1 8 out xtal osc gnd y1 7 r9 2.2k 5v rreset r10 2.2k ffqud r11 2.2k wwclk r3 2.2k strobe figure 17. ad9850/cgpcb electrical schematic component list integrated circuits u1 ad9850brs (28-lead ssop) u2, u3 74hct574 h-cmos octal flip-flop capacitors c1 470 pf ceramic chip capacitor c2 to c5, c8 to c10 0.1 f ceramic chip capacitor c6, c7 10 f tantalum chip capacitor c11 22 pf ceramic chip capacitor c12 3.3 pf ceramic chip capacitor c13 33 pf ceramic chip capacitor c14 8.2 pf ceramic chip capacitor c15 22 pf ceramic chip capacitor resistors r1 3.9 k resistor r2 50 resistor r3, r9, r10, r11 2.2 k resistor r4, r5 100 k resistor r6, r7 200 resistor r8 100 resistor connectors j2, j3, j4 banana jack j5 to j9 bnc connector inductors l1 910 nh surface mount l2 680 nh surface mount
ad9850 e18e rev. h 18a. ad9850/cgpcb top layer 18b. ad9850/cgpcb ground plane 18c. ad9850/cgpcb power plane 18d. ad9850/cgpcb bottom layer figure 18. ad9850/cgpcb evaluation board layout
ad9850 e19e rev. h outline dimensions 28-lead shrink small outline package [ssop] (rs-28) dimensions shown in millimeters 0.25 0.09 0.95 0.75 0.55 8 4 0 0.05 min 1.85 1.75 1.65 2.00 max 0.38 0.22 seating plane 0.65 bsc 0.10 coplanarity 28 15 14 1 10.50 10.20 9.90 5.60 5.30 5.00 8.20 7.80 7.40 compliant to jedec standards mo-150ah
ad9850 e20e rev. h e20e c00632e0e2/04(h) revision history location page 2/04?data sheet changed from rev. g to rev. h. changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 12/03?data sheet changed from rev. f to rev. g. changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 changes to table i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 11/03?data sheet changed from rev. e to rev. f. renumbered figures and tpcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 updated ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

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